1. Field of the Invention
The present invention relates to the testing of semiconductor memory devices, and more specifically to a semiconductor memory device and method for reducing a number of input cycles needed to input a test pattern, and thereby shortens the testing time and also simplifies the test pattern.
2. Description of the Related Art
Semiconductor memory devices are tested to ensure that they operate properly. To test memory devices, a test pattern including a command and an address, as well as test data, should be provided therewith. When a serial access memory is tested, the command and the address must be serially inputted over a plurality of input cycles.
FIG. 1 shows a block diagram of a typical conventional serial access memory device. The memory device includes an I/O buffer 102, a command register control circuit 103, an address register control circuit 104, a register control clock generator 105, an address increment clock generator 106, command registers 1071-107N, a command decoder 108, address registers 1091-109M+L, counters 1101-110M, an address decoder 112, and a memory cell array 113. The memory cell array 113 includes a plurality of memory cells arranged in rows and columns.
The I/O buffer 102 receives external I/O signals I/O0-I/OPxe2x88x921 developed by an external circuit (not shown). The I/O signals I/O0-I/OPxe2x88x921 sequentially transfer a test pattern including a command and an initial address.
The command is represented by N command values, and the initial address is represented by (M+L) initial address values, where N, M, and L are an integer. The N, M, and L are determined on the basis of the scale of the memory device.
Each of the N command values and the (M+L) initial address values are constituted by P bits, each of which is respectively associated with I/O signals I/O0-I/OPxe2x88x921. Hereinafter, each of the N command values is respectively denoted by command values CM1-CMN, and each of the (M+L) initial address values is respectively denoted by initial address values AR1-ARM+L. The command values CM1-CMN are respectively outputted to the command registers 1071-107N, and the initial address values AR1-ARM+L are respectively outputted to the address registers 1091-109M+L.
The command register control circuit 103 sequentially activates the command register 1071-107N in response to a register control signal 103a provided by an external circuit (not shown). The activation of each of the command register 1071-107N is respectively synchronized with the inputs of the command values CM1-CMN.
The address register control circuit 104 sequentially activates the address registers 1091-109M+L in response to a register control signal 104a provided by an external circuit (not shown). The activation of each of the address registers 1091-109M+L is respectively synchronized with the inputs of the initial address values AR1-ARM+L.
The register control clock generator 105 is responsive to an external clock signal 105a for developing a register control clock signal 105b. The register control clock signal 105b is outputted to the command registers 1071-107N and the address registers 1091-109M+L.
The address increment clock generator 106 is responsive to another external clock signal 106a for developing an address increment clock signal 106b. The address increment clock signal 106 is outputted to the counters 1101-110M.
The command registers 1071-107N are sequentially activated by the command register control signal 103b to respectively latch the command values CM1-CMN. The latching of the command values is executed in synchronization with the register control clock signal 105b. The command registers 1071-107N respectively outputs the latched command values CM1-CMN to the command decoder 108.
The command decoder 108 decodes the command values CM1-CMN to generate a command that determines an access mode of an access to the memory cell array 112. The command decoder 108 informs the counter 1101-110M of the generated command.
The address registers 1091-109M+L are sequentially activated by the address register control signal 104b to respectively latch the initial address values AR1-ARM+L. The latching of the initial address values AR1-ARM+L is executed in synchronization with the register control clock signal 105b. The address registers 1091-109M respectively output the initial address values AR1-ARM+L to the counter 1101-110M, while the remaining address registers 109M+1-109M+L respectively output the initial address values ARM+1-ARM+L to the address decoder 112. The initial address values AR1-ARM is representative of a lower address of the initial address, while the initial address values ARM+1-ARM+L are representative of an upper address of the initial address. In a serial access of the memory cell array 113, the upper address of the accessed memory cells is fixed to the initial upper address represented by the initial address values ARM+1-ARM+L. Therefore, the initial address values ARM+1-ARM+L may be denoted by address values AARM+1-AARM+L which are representative of an upper address of the accessed memory cells in the following.
The counters 1101-110M respectively generate address values AAR1-AARM which are representative of a lower address of the memory cell to be accessed in the memory cell array 112. The counters 1101-110M respectively receive the initial address values AR1-ARM from the address register 1091-109M to initialize the address values AAR1-AARM respectively to the initial address values AR1-ARM before a serial access to the memory cell array 112 is started. During the serial access, the counters 1101-110M respectively increment the address values AAR1-AARM, and thereby increment the lower address of the accessed memory cell. The counters 1101-110M also controls the address values AAR1-AARM in responsive to the command determined by the command decoder 108. The counters 1101-110M output the address values AAR1-AARM.
The address decoder 112 receives the address values AAR1-AARM from the counter 1101-110M and the address values AARM+1-AARM+L (which are respectively same as the initial address values ARM+1-ARM+L) from the address registers 109M+1-109M+L. The address decoder 112 decodes the address values AAR1-AARM+L to allow one of the memory cells in the memory cell array 113 to be accessed.
FIG. 2 is a timing chart showing the operation of a conventional serial access memory device. At first, the command register control signal 103a is activated for a period from a time S to a time T. The command register control circuit 103, in response to the command register control signal 103a, sequentially activates the command registers 1071-xcfx89N, while the command values CM1-CMN are sequentially inputted to the I/O buffer 102. The command registers 1071-107N respectively latch the command values CM1-CMN in synchronization with the register control clock signal 105b. The command decoder 108, in response to the command values CM1-CMN, outputs a command that determines an operating mode. The serial input of the command values CM1-CMN requires N input cycles of the register control clock signal 105b. 
Then, the address register control signal 104a is activated for a period from time T to time V. The address register control circuit 104, in response to the address register control signal 104a, sequentially activates the address registers 1091-109M+L, while the initial values AR1-ARM+1 are sequentially inputted to the I/O buffer 102. The address registers 1091-109M+L respectively latch the initial address values AR1-ARM+L in synchronization with the register control clock signal 105b. The serial input of the initial address values AR1-ARM+L requires M+L input cycles of the register control clock signal 105b. 
The counters 1101-110M respectively latch the initial address values AR1-ARM and respectively initialize the address values AAR1-AARM to the initial address values AR1-ARM. As mentioned above, the address values AARM+-AARM+L, which are representative of the upper address, are respectively the same as the initial address values ARM+1-ARM+L. These result in that the address of a firstly accessed memory cell is set to be the initial address represented by the initial address values AR1-ARM+L.
Then the serial access to the memory cell array 113 is started at the time W. The address decoder 112 selects one of the memory cells on the basis of address values AAR1-AARM+1, and allows the selected memory cell to be accessed. After every access to the memory cells, the address values AAR1-AARM are increased by the counters 1101-110M such that the accessed address is incremented. The increment of the accessed address achieves serial access to the memory cell array 113. In a read mode, the data stored in the memory cell array 113 is sequentially outputted.
In a memory device, the N command values and the (M+L) initial address values are serially inputted, and thus the input of the command values and initial address values requires (N+M+L) input cycles. That is, N input cycles for the command input and (M+L) input cycles for the initial address input.
The serial input increases the number of input cycles needed to input the test command and test address, and thus increases the testing time. The number of the input cycles tends to increase because of the progress in the function of the memory device and the increase in the capacity of the memory device. The increase of the number of input cycles is a serious problem, especially in a memory device having a small number of I/O pins therein. Also, the increase of the number of input cycles is enhanced as the memory devices increase in capacity and function.
Also, there is a limitation on the number of input cycles in a tester, especially, a tester for testing the durability of the device.
Therefore, it is desired that a number of input cycles needed to input a command and an address is reduced.
As another related technique, a built-in self-test (BIST) technique is widely known. A BIST circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-184989). The BIST circuit includes an internal clock generator, an internal address generator, and a test pattern generator and a comparator.
Another built-in self test (BIST) circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-39226). A conventional memory device is provided for determining an address and a bit of a failed memory device without an increase in testing time and cost. The conventional memory device also enables the easy testing of an AC property, such as an access time.
A semiconductor device is provided with a memory including memory cells and a BIST circuit for testing the memory.
The BIST circuit is composed of a controller, an address generator, a data generator, a comparator, a scanning circuit, and a multiplexer. The controller outputs a control signal in response to a test start signal in synchronization with a test clock. The address generator provides an address signal for the memory in response to the control signal. The data generator provides test data for the memory cells in response to the control signal. The test data is read out from the memory cells. The comparator compares the actual read out data with the known input test data, and outputs an error signal if the input test data and the actual data are different from each other. The scanning circuit serially outputs the actual read out data and the address signal. The multiplexer selectively outputs the error signal from the comparator or outputs the actual read out data and the address signal from the scanning circuit in response to the control signal. When the comparator outputs the error signal, the actual read out data associated with the error signal is outputted from the multiplexer, and the address signal associated with the actual read out data is outputted from the multiplexer.
Still another conventional memory device including a BIST circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-245498). The BIST circuit enables a profound function test with a simple configuration.
A memory device is provided with a memory cell array including memory cells, an address generator, a data storage circuit, and a test circuit. The address generator generates an address signal for addressing the memory cell array. The data storage circuit stores data and transfers it to or from the memory cell array. The test circuit, in response to a test mode signal, writes a test pattern to the memory cell array by controlling the address generator and the data storage circuit. The test circuit enables an automatic test including a series of write and read.
Yet still another memory device including BIST circuit for reducing a chip area thereof is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-162600). A memory device is provided with a memory cell and a BIST circuit. The BIST circuit includes a test clock generator, a column address counter, a low address counter, a data generating and comparing circuit, a timer, and a sequencer. The test clock generator generates a test clock that times the operation of the BIST circuit. The column address counter provides a column address of the memory cell to be accessed. The low address counter provides a row address of the cell to be accessed. The data generating and comparing circuit provides a test data for the memory cell array, and compares the read out data from the memory cell array with the input test data. The timer measures the time needed to test the memory cell array. The sequencer controls the test clock generator, the column address counter, the low address counter, the data generating and comparing circuit, and the timer. The sequencer is constituted by a sequential circuit, and thus the chip area of the memory device is reduced.
Still another memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-28853). The memory device enables secret protection of a software program during testing.
The memory device is provided with a built-in memory including having a program memory, an address generator, an address decoder for generating an address of the program memory; an output circuit for reading out data stored in the program memory, a test controller for outputting an address control signal for controlling the address in response to a test signal, and an address controller for controlling the address control signal in the test control circuit so as to turn off the address control signal when the address becomes a predetermined address.
The object of the present invention is to provide a memory device for reducing input cycles needed to input a test pattern.
Another object of the present invention is to provide a memory device for simplifying a test pattern.
Still another object of the present invention is to provide a memory device for reducing the testing time.
In order to achieve an aspect of the present invention, a memory device is composed of a memory cell array including a plurality of memory cells, an I/O buffer, a command providing unit, an address providing unit, and an address decoder. The command providing unit is responsive to a test mode signal for providing a command that controls access to the memory cell array. The address providing unit provides an address in response to the command. The address decoder allows the memory cell array to be accessed in response to the address. The command providing unit sets the command to a predetermined internal command when the test mode signal is activated. The command providing unit, when the test mode signal is not activated, receives an external command through the I/O buffer and sets the command to an external command.
When the command providing unit includes a command register storing a command value, and a command decoder decoding the command value to generate the command, it is desirable that the command register fixes the command value to a predetermined command value when the test mode signal is activated, and that the command register latches an external command value representative of the external command to set the command value to be the external command value.
Also, the command providing unit preferably includes a command register storing a command value, the command register latching through the I/O buffer an external command value representative of the external command, and a command decoder, the command decoder fixing the command to a predetermined command when the test mode signal is activated, and the command decoder decoding the command value to generate the command when the test mode signal is not activated.
The address providing unit may initialize the address to an initial address before the access and increment the address from the initial address during the access. In this case, It is preferable that the address providing unit, when the test mode signal is activated, fixes the initial address to a predetermined initial address, and when the test mode signal is not activated, the address providing unit receives an external initial address through the I/O buffer and sets the initial address to be the external initial address.
The address providing unit preferable includes an address register storing an initial address, the address register fixing the initial address to a predetermined initial address when the test mode signal is activated, and the address register receiving an external initial address through the I/O buffer to set the initial address to be the external initial address, and an address increment unit which provides the address, the address increment unit initializing the address to the initial address before the access, and the address increment unit increasing the address during the access in response to an address increment clock signal.
When the address includes an upper address, and a lower address, and the address providing unit preferably includes an upper address register storing the upper address, a lower address register storing an initial lower address, the lower address register fixing the lower initial address to a predetermined lower initial address when the test mode signal is activated, and the address register receives an external initial lower address through the I/O buffer to set the initial lower address to be the external initial lower address, and a counter providing the lower address, the counter initializing the lower address to the initial lower address value before the access and the counter increasing the lower address from the initial lower address in response to an address increment clock signal.
In this case, the first address register preferably receives an external upper address whenever the test mode signal is activated or not.
It is also preferable that the first address register fixes the upper address to a predetermined upper address when the test mode is activated, and that the first address register receives an external upper address through the I/O buffer to initialize the upper address to the external upper address when the test mode is not activated.
In order to achieve another aspect of the present invention, a memory device is implemented with a memory cell array including a plurality of memory cells, an I/O buffer, an address providing unit, and an address decoder. The address providing unit is responsive to a test mode signal for providing an address. The address providing unit initializes the address to an initial address before an access to the memory cell array, and increments the address from initial address during the access. The address decoder allows the memory cell array to be accessed in response to the address. The address providing unit, when the test mode signal is activated, fixes the initial address to a predetermined initial address, and, when the test mode signal is not activated, the address providing unit receives an external initial address through the I/O buffer to set the initial address to be the external initial address.
The address providing unit preferably includes an address register storing the initial address, the address register fixing the initial address to a predetermined initial address when the test mode signal is activated, and the address register receiving an external initial address through the I/O buffer to set the initial address to be the external initial address, and an address increment unit which provides the address, the address increment unit initializing the address to the initial address before the access, and the address increment unit increasing the address during the access in response to an address increment clock signal.
When the address includes an upper address and a lower address, the address providing unit preferably includes an upper address register storing the upper address, a lower address register storing an initial lower address, the lower address register fixing the lower initial address to a predetermined lower initial address when the test mode signal is activated, and the address register receives an external initial lower address through the I/O buffer to set the initial lower address to be the external initial lower address, and a counter providing the lower address, the counter initializes the lower address to the initial lower address value before the access and the counter increasing the lower address from the initial lower address in response to an address increment clock signal.
The first address register preferably receives an external upper address whenever the test mode signal is activated or not.
It is also preferable that the first address register fixes the upper address to a predetermined upper address when the test mode is activated, and the first address register receives an external upper address through the I/O buffer to initialize the upper address to the external upper address when the test mode is not activated.
In order to achieve still another aspect of the present invention, a method of operating a memory device is composed of:
providing a test mode signal;
providing a command which controls access to a memory cell, providing the command including:
setting the command to be a predetermined internal command when the test mode signal is activated, and
setting the command to be an external command received from an external circuit when the test mode signal is not activated;
providing an address in response to the command; and
allowing the memory cell array to be accessed in response to the address.
In order to achieve yet still another aspect of the present invention, a method of operating a memory device is composed of:
providing a test mode signal;
providing an address for access to a memory cell array;
allowing the memory cell array to be accessed in response to the address, the providing the address including:
initializing the address to a predetermined initial address before the access when the test mode signal is activated;
initializing the address to an external initial address received from an external circuit before the access when the test mode signal is not activated;
incrementing the address during the access.